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1/25 october 2001 AN1178 application note 80c32/psd8xx design guide contents n in-system programming and in-application re- programming C the iap problem C a common solution n physical connections n simple design example C memory map C psdsoft express design entry n enhanced design example C memory map C psdsoft express design entry n conclusion n references n appendix a: connecting to a psd813f with no boot memory easy flash ? psd8xx devices are members of a family of flash memory-based peripherals for use with embedded mi- crocontrollers (mcus). these programmable system devices (psds) consist of memory, logic, and i/o. when coupled with a low-cost 80c32 mcu, the psd forms a complete embedded flash memory system that is 100% in-system programmable (isp) and in-application programmable (iap). there are many features in the psd silicon and in the psdsoft express devel- opment software that make isp easy, regardless of how much experience you have with embedded design. this document offers two designs using a psd813f1 and an intel 80c32 mcu. note that a variety of 8-bit mcu/mpus can be used in place of the intel part. although the specifics of this document are based on the 80c32, this document can be used as a guide for other mcu/mpu applications. the first design is a simple system to get up and running quickly for basic appli- cations or to check out your prototype 80c32 hardware. the second design illustrates the use of enhanced features of psd in-system programming as applied to the 80c32. you can start with the first design and migrate to the second as your function- al requirements grow. there are other members of the psd8xx family, including the psd813f1/f3/f4/f5, the psd833f2/834f2, and the psd835g2. see the selector guide on the website for a comparison of the products. this applica- tion note is applicable to all psd8xx family members. in-system programming and in-application re- programming our industry uses the term in-system programming (isp) in a general sense. isp is applicable to programmable logic, as well as programmable non-volatile memory (nvm). however, an additional term will be used in this document: in-application programming (iap). there are subtle yet significant differences between isp and iap when microcontrollers are involved. isp of memory means that the mcu is off-line and not involved while memory is being programmed. for iap, the mcu partici- pates in programming the memory, which is important for sys- tems that must be online while updating firmware. often, isp is well suited for manufacturing, while iap is appropriate for field updates. psd8xx devices are capable of both isp and iap.
AN1178 - application note 2/25 keep in mind that iap can only program the memory sections of the psd and not the configuration and programmable logic portions. with isp, the entire psd can be erased or programmed. the iap problem typically, a host computer downloads firmware into an embedded flash memory system through a com- munication channel that is controlled by the mcu. this channel is usually a uart, but any communication channel that the 80c32 supports will do. the 80c32 must execute the code that controls the iap process from an independent memory array that is not being erased or programmed. otherwise, boot code and flash memory programming algorithms (iap loader code) will be unavailable to the 80c32. it is absolutely necessary to use an alternate memory array (an independent memory that is not being programmed) to store the iap loader code. a system designer must choose the type of alternate memory to store iap loader code (rom, sram, flash, or eeprom); each type has advantages and disadvantages. this alternate memory may reside external to the mcu or on-chip. a top-level view of an embedded iap flash system with external memory is shown in figure 1. figure 1. embedded flash system capable of iap (5 devices) another problem, which is specific to the 80c32 architecture, is related to the separate program and da- ta address spaces. the 80c32 cannot write to program space, but that is where the flash memory re- sides that holds 80c32 firmware. how can one program flash memory in-system if the 80c32 cannot write to program space? a common solution without a psd device, implementing iap with the 80c32 can be difficult and time consuming. philips ap- plication note an440 contains a ram loader program (bootstrap loader). it shows how to load code into an external ram over a serial link after power-up and how to switch execution to that ram to complete the boot sequence. this can be a cumbersome and error prone exercise using re-locatable code in volatile memory, which is difficult to debug, vulnerable to power outages, and not supported by all emulators. ad- ditionally, this method restricts the designer to using a uart to implement iap. to overcome the issue of program versus data space, a common practice is to combine the two address spaces, which reduces the total address space of the 80c32 by 50%. a better, integrated solution figure 2 shows a two-chip solution using an easy flash psd813f. this system has ample main flash memory, a second alternate flash memory to hold the iap loader code and general data, and more sram. all three of these memories can operate independently and concurrently; meaning the mcu can operate from one memory while erasing/writing the other. this allows the mcu to continue normal oper- ai03339b embedded system system i/o cpld 80c 32 host computer communication channel main flash memory 128 kbytes alternate memory for isp loader code system sram 8 kbytes
3/25 AN1178 - application note ation during iap, which is crucial for some applications. this system also has programmable logic, ex- panded i/o, and design security. the two chip solution is 100% programmable in the factory or in the field. figure 2. embedded flash system capable of isp (2 devices) note: 1. other members of the psd8xx family offer more flash memory and more sram. 2. only the psd813f1 offers eeprom, while the other members of the psd8xx family offer secondary flash memory. by design, the iap method described above requires mcu participation to exercise a communication channel to implement a download to the main flash memory. the psd8xx also offers an alternative method called in-system programming (isp) to program the psd using a built-in ieee 1149.1 jtag in- terface requiring no mcu participation. this means that a completely blank psd can be soldered into place and the entire chip can be programmed in-system in just a few seconds using sts flashlink? jtag cable and psdsoft express development software. no 80c32 firmware needs to be written. just plug in the flashlink cable to your pcs parallel port and begin programming memory, logic, and config- uration. this is a powerful feature of the psd8xx that allows immediate development of application code in your lab, smart manufacturing techniques, and easy field updates. the flashlink? cable and psdsoft express software are available in a kit from the website www.st.com/ psd . ai03340b embedded system system i/o jtag 80c32 host computer communication channel 128 kbyte flash optional 32 kbyte eeprom/flash optional 2kbyte sram programmable logic i/o psd813f
AN1178 - application note 4/25 figure 3. top level block diagram of psd813f physical connections connect your 80c32 to the psd8xx as shown in figure 4 (next page). the same connections can be used for all of the members of the psd8xx family except the psd835g2, which has more i/o. the jtag programming channel, sram with battery backup, lcd module, and mcu i/o connections are all option- al. this example design is similar to sts dk900 development kit, available for purchase on the web: www.st.com/psd . there are 13 unused psd i/o pins in this example. unused pins should be pulled to vcc with a 100k resistor or tied to gnd. see application note an1153 for more information on the jtag port. ai03322b jtag controller cpld 16 output macrocells 24 input macrocells 128 kbyte flash 8 sectors decode pld optional 2 kbyte sram optional 32 kbyte eeprom/flash 4 sectors page reg power mngt device security mcu control mcu address / data pld bus i/o bus i/o port a i/o port b i/o port c i/o port d mcu address / data / control bus psd813f
5/25 AN1178 - application note figure 4. physical connections, 80c32 and psd813f simple design example the first design example outlines the steps required to get a 80c32 system up and running quickly. a con- nection diagram, memory map, and the necessary design file for the psdsoft express software develop- ment environment are provided. a psd813f2 was used for this example. however, other members of the easy flash ? family may be used instead, with minor changes to the sample design file. see the selector guide on the website for a comparison of the products. memory map for this simple design, we used a psd813f2 with the following memories: 128 kbyte main flash memory, broken into eight 16 kbyte segments denoted fs i (i = 1-8) 32 kbyte secondary flash memory, broken into four 8 kbyte segments denoted csboot j (j = 1-4) . (the psd813f1 has a boot eeprom instead of flash memory. therefore, ees j (j = 1-4) would be used in place of csboot j .) 2 kbyte sram (rs0) 256 byte psd813f configuration register (csiop). note: the psd memory segments are defined in the chip select equations screen in psdsoft express. well use the boot memory to hold the isp boot loader code, 80c32 interrupt vectors, and common firm- ware functions. for this example, well execute from secondary flash memory only and leave the main flash memory in data space. lets examine the sample memory map in figure 5, below: ai03341b tdo tstat ad1 tms ad2 ad6 terr\ ad3 ad0 ad7 ad4 tdi ad5 tck rwlcd mcuio2 mcuio3 reset\ cslcd mcuio1 mcuio0 rslcd a14 a12 a15 a9 a13 wr\ as a8 a10 a11 psen\ rd\ u2 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 46 20 19 18 17 14 13 12 11 47 50 49 10 9 8 48 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 adio15 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 cntl0 cntl1 cntl2 pd0 pd1 pd2 reset u1 ea xtal1 xtal2 rst int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 rd psen ale txd rxd wr reset int0\ int1\ reset\ data bus 2 x 16 lcd module jtag-isp connector rs r/w e mcu i/o signals xx mhz uart port spare i/o reset cslcd ad7-ad0
AN1178 - application note 6/25 figure 5. memory map, simple 80c32/psd813f design keep the following in mind about the sample memory map shown in figure 5: yellow (shaded) indicates memory that is common to all pages. it is broken up into two 64 kbyte spaces: program and data space. the 32 kbytes of the psd813f boot memory is mapped to program space. (there are several references to boot memory in this document, but the boot memory is simply a secondary memory that can be used as boot memory or can serve any other purpose.) the main flash memory is mapped to data space so that the contents can be programmed. all of main flash memory is paged because of the limited address range of the 80c32. the psd control register and sram are located at the bottom of data space. note that placing the main flash memory and secondary memory into program space or data space is accomplished with the psd vm register. psdsoft express is used to define the initial value of the vm register when the system powers up or is reset. this initial value is stored in the fusemap that gets pro- grammed into the psd. at runtime, the vm register can be changed by writing to it with the mcu. this is illustrated in the enhanced design of section 4. the boot memory holds the following vectors and code: 80c32 reset vector and initialization routines 80c32 interrupt vectors and service routines i/o management since figure 5 is a sample memory map, you may wish to change it. to do so, simply change the chip select equations within the design assistant in psdsoft express. for example, if you have a psd813f 0000 2000 ffff 4000 ffff 2800 8000 c000 0000 0300 0200 2000 0400 6000 8000 ai03342b not to scale boot from here program space data space unmapped 32 kbytes csboot3/ees3 optional boot flash/eeprom 8 kbytes csboot2/ees2 optional boot flash/eeprom 8 kbytes csboot1/ees1 optional boot flash/eeprom 8 kbytes csboot0/ees0 optional boot flash/eeprom 8 kbytes unmapped 22 kbytes fs0 page 0 16 kbyte fs2 page 1 16 kbyte fs1 page 0 16 kbyte fs3 page 1 16 kbyte fs4 page 2 16 kbyte fs6 page 3 16 kbyte fs5 page 2 16 kbyte unmapped psd control register (csiop) 256 bytes optional sram (rs0) 2 kbytes 8xc51 ram fs7 page 3 16 kbyte lcd chip select (cslcd) 256 bytes
7/25 AN1178 - application note part that doesnt contain the optional secondary memory, you will want to have the main flash memory located in program space. see appendix a for a sample memory map for parts with no secondary boot memory. psdsoft express design entry highlights of design entry will be given here. please refer to the psdsoft express user manual for a thor- ough coverage of all the features of psdsoft express. this section is meant to show you just the essentials to get you going. here are the steps: invoke psdsoft express and open a new project. start psdsoft express. create a new project. select your project folder and name the project (in this example, name the project easy8051 in the folder psdsoft\my_project). mcu and psd selection. when you click ok in the new project window, the mcu and psd selec- tion screen appears. when you see this screen, make the following selections: select an mcu manufacturer and part number. in this example, were using an intel 8xc32. notice how the control signals are selected for you in this case. select the psd8xx series for the psd family. select a psd813f2 and use the 52-pin plcc package (j package). based on the above selections, the bus width, bus mode, and ale/as active level will be set auto- matically. set the main flash memory to data space only and the secondary flash memory to program space only. this is what the screen should look like after youve made the selections:
AN1178 - application note 8/25 now you have your project established based on a psd813f2 and an 80c32. however, there are many other mcu/mpus you could have chosen in place of the 80c32 and still have use of this document. note that this template will work in our dk900 development kit. click ok and the design parameters window will appear. design parameters . choose use example template selection and click ok to be taken to the mcu template selection screen.
9/25 AN1178 - application note mcu template selection. for the simple design, we will use paging, but will not be swapping memory locations. as such, you should pick iap, with memory paging and click generate to be taken to the pin definitions screen. again, this template matches the requirements of the dk900 development kit. pin definitions. your pin definitions should match the screen below and are setup according to the phys- ical connections shown in section 2. on this screen, you can add or update pin functionality as desired. click next >> to be taken to the design assistant screen. note: there are detailed instructions on how to use this screen and other design assistant screens in the psdsoft express user manual .
AN1178 - application note 10/25 page register definition. looking at the memory map in figure 5, we see that wee will need four mem- ory pages, so we need to define two page register bits (2 2 = 4). since you selected the template previ- ously, the page register definition should match the one shown below. later, you will see how the page register can be used for general logic inputs to the pld. click next >> when finished.
11/25 AN1178 - application note chip select equations. use this screen to enter chip-select equations to match your memory map. the chip select equations shown should match the memory map of figure 5. note the page number associa- tion for the fs0-7 segment selects. click next >> when finished.
AN1178 - application note 12/25 i/o logic and user defined node equations. the i/o logic equations and user defined node equations screens are used to enter equations for the registered logic within the psd. since this docu- ment focuses on issues related to isp and iap, registered logic equations are not covered. however, for more information on entering registered logic equations, refer to the psdsoft express user manual . also, see application note an1356 design guide: psdsoft express , for a tutorial on implementing logic in the cpld. click done and the software will check your design for errors (which there should be no errors using the template). you should now see the design flow window: click on additional psd settings in the design flow window and a dialog box will appear. additional psd settings. there are three functions that can be accomplished in this dialog box: 1. setting the security bitblocks all access to the contents of the psds memories by means of jtag or a conventional programmer. that is, once the security bit is set, no programmer can read or copy the configuration or memory contents of the psd. the only way to erase the security bit is to completely erase the psd. 2. specify the ieee 1149.1 jtag user codeallows you to enter a 32-bit code which can be used for var- ious functions. click on the jtag/isp tab for more details 3. set the internal memories sector protectionsallows the individual memory sectors within the psd to be write protected to prevent accidental data loss. the mcu/mpu cannot change these settings at run- time; only a device programmer can alter these settings. click ok and you will see the design flow again. next, we need to fit the design to silicon. fitting the design to silicon. to fit the design to silicon, click the fit design to silicon box in the de- sign flow. psdsoft express will compile and synthesize the design and create part of the program data
13/25 AN1178 - application note file (.obj) that will later be programmed into the psd813f2 silicon. when this process is complete, a report will pop up that shows the resulting pin assignments psd usage. this is the fitter report, which you can use to document your design. since this design is based on a template, you should receive no errors dur- ing the fitting process. however, if you create a project from scratch and receive a fitter error, you should check the psdsoft express user manual for further instructions. c code generation. you can take advantage of the provided low-level c code for accessing memory el- ements within the psd by clicking on the generate c code specific to psd box in the design flow win- dow. to get the c functions and headers, specify the folder in which you want the ansi c files to be written. ansi c code functions and headers are generated for you to paste into your 80c32 c compiler environment in the folder you specify. simply tailor the code to meet your system needs. see the psdsoft express user manual for details on the c code generation feature. merge mcu firmware with psd. now that the fitting process is complete, psdsoft express has created a fuse pattern that reflects the psd configuration and logic of your design. psdsoft express places this fuse information into a file (the .obj file). however this fuse pattern does not yet contain the 80c32 firm- ware. the next step will accomplish this, producing an .obj file that contains the psd configuration and the 80c32 firmware. this final .obj file is what gets programmed into the psd. the same .obj file is appended with mcu firmware in the next step below. for this step, merge mcu firmware with psd, you will input the firmware file(s) that contain absolute addresses from your 80c32 compiler/linker in intel hex format. the merger will map these file(s) into the memory segments of the psd according to the chip select equations that you entered in the design as- sistant. this mapping process translates the absolute system addresses that 80c32 uses into physical internal psd addresses that are used by a programmer to program the psd. the address translation pro- cess is transparent. all you need to do is enter the file(s) that were generated from your 80c32 linker into the appropriate boxes and psdsoft express does the rest. go to the design flow window and click the merge mcu firmware with psd box. you should see the following warning as the utility starts: for this example, you can ignore this warning and click ok because we are only placing 80c32 code into boot flash memory segments csboot0 and csboot1, which are not paged. here is an explanation of the warning in case you use paging in future designs: psdsoft express attempts to populate all of the address range boxes for you, based on your chip select equations. these are the absolute address ranges that psdsoft express will expect to see inside the file(s) generated by your 80c32 linker. however, if psdsoft express sees that paging information is used in your psd memory segment equations, psdsoft express warns you it has filled in address ranges that
AN1178 - application note 14/25 may be ambiguous (overlapping or dependent on non-address signals, like page register bits) and it is up to you to resolve them. how you resolve them is purely a function of your 80c32 compiler/linker and how it handles paging. for example, some mcu linkers will generate a different file for each memory page of firmware, and each of these files will contain mcu addresses that do not exceed 16 bits. other linkers will put all of the memory pages of firmware into a single file using mcu addresses greater than 16 bits to represent multiple pages (extends 16-bit addresses with page bits). either method requires you to type the appropriate file name(s) and address ranges into the window based on how your particular 80c32 link- er operates. after clicking ok , you should see this: the far left column contains individual psd memory segments. the next column shows the logic equa- tions for selection of each memory segment (shown for reference only). in the middle are the address ranges that were specified in the chip select equations screen to create the memory map. psdsoft ex- press filled in these address fields for you. psdsoft express expects to find these absolute mcu address- es within your 80c32 linker file(s) when they are imported. on the right are boxes where you can type in (or browse for) the name of the file(s) (including path) that indicates the location of your 80c32 linker files. notice that you can select motorola s-record or intel hex record for the input type. leave the mapping mode set to direct. now slide the scroll bar down until you see csboot0 and csboot1.
15/25 AN1178 - application note type in the name of the file from your 80c32 linker that contains the firmware that will boot up your system. click the browse button and go to the examples directory and select isp_8032.hex. this file contains very simple 80c32 code that configures your dk900 system hardware and performs rudimentary tasks to check out your system. in this example, there are 16 kbytes available in boot flash memory segments csboot0 and csboot1, which is more than enough for this simple boot and test code. after your new hard- ware is tested, you can add more code to the boot area for advanced tasks, such as implementing a down- load to main flash memory from a host computer, as shown in the enhanced design of the next section. no file names are required for the main flash memory regions (fs0-fs7) because we are only operating out of secondary flash memory for now. click ok , and the address translate process will produce the final programming data file (.obj) that can be used to program the psd. programming the psd. the .obj file can be programmed into the psd in one of three ways: the flashlink ? jtag cable, which connects to the pc parallel port. the st psdpro device programmer, which also connects to the pc parallel port. third-party programmers, such as stag and needhams. see the website at www.st.com/psd for a list of compatible third-party programmers. first well show you how to use the flashlink ? jtag cable to program the psd. programming with flashlink ? . connect the flashlink ? cable to your pcs parallel port. click the
AN1178 - application note 16/25 st jtag/isp box in the design flow window. you will be prompted for the number of devices in the jtag chain on your circuit board. make the appropriate selection and click ok . this document assumes only one device is in the jtag chain. if you have more than one device, refer to the psdsoft express user manual . for single device jtag chains, the window will look similar to the following one: to use this window, ensure that the correct programming data file and psd device appear in step 1. for step 2, select the desired operation, the regions of the psd that the operation affects, and the number of jtag pins (4 or 6) to use on the circuit board. the template assumes all six pins will be used. before you perform the selected operation, click the properties button. this dialog box allows you to do the following: set port pins: with this screen, you can set up the psds i/o pins during jtag operations. the default (except for the jtag pins) is input, which is usually fine for most pins. (note that the psd will not respond to any non-jtag i/o.) however, sometimes it may be desirable to set a pin or pins to output during jtag. for example, if you have chip-select signal being generated from the psd that selects a device that po- tentially could drive signals on the jtag lines (if you are multiplexing the pins), you would want that chip- select to be inactive during the jtag operation. jtag-isp attributes: this screen allows you to view the device name and instruction register length. this information may be useful to other design programs. user code: basically, by clicking on the user code tab, you are provided with a space to enter an ieee 1149.1 user code that will be compared to the value previously entered in the additional psd settings screen. once you are satisfied with your property settings, click ok to return to the jtag-isp operations win- dow. you can now perform the selected operation by clicking execute . before you leave this screen, you may wish to save your jtag configuration. this can be done in step 3 by clicking on the save button and specifying a file name. this file can be used next time by clicking the retrieve button. programming with psdpro. ensure that the psdpro device programmer is connected to your pcs par- allel port. click on the st conventional programmers box in the design flow window. you will see this:
17/25 AN1178 - application note if this is the first use of the psdpro, click on the htest icon to perform a test of the psdpro and the pc port. after testing, place a psd813f2 into the socket of the psdpro and click on the program icon. (the .obj file is automatically loaded when this process is invoked). the messaging of psdsoft express will in- form you when programming is complete. this window is also helpful even if you do not have a psdpro programmer. you can use this window to see where the merge mcu firmware utility of psdsoft express has placed the 80c32 firmware within physical memory of the psd. for this design example, you can click on the secondary flash memory icon in the tool bar. notice the 80c32 reset vector at absolute mcu addresses 0000h and 0002h, translates to psd secondary flash memory physical addresses 20000h and 20002h, respectively. to see how all of your 80c32 absolute addresses translated into physical psd memory addresses, click report->address translation . the start and stop addresses in the report are the absolute mcu system addresses that you have specified. the addresses shown in square brackets are direct physical addresses used by a device programmer to access the memory elements of the psd in a linear fashion (a special device programming mode that the mcu cannot access). enhanced design example this second design example builds upon the first to add enhanced features to this isp/iap capable sys- tem. the physical connections between the 80c32 and psd813f2 do not change, but the memory map and chip select equations do. the focus of this enhanced design is to show how the memories of the psd813f2 can be used concurrently. this means swapping the boot code out of program space after the initial boot sequence has completed. the boot code can then be updated if desired. memory map the boot sequence and memory swap is a four-step process, as shown in figure 6 to figure 9. the re- quired changes in psdsoft express are explained after that (section 4.2). memory map configuration at boot-up. figure 6 (next page) shows how the memory map looks at system power-on or at system reset. the swap bit is one of the eight internal psd page register bits, whose value is zero by default. the swap bit is an example of how the page register bits can be imple- mented for uses other than memory paging. the vm register controls which space (program or data) the
AN1178 - application note 18/25 psd memories appear in and can be set prior to runtime using psdsoft express configuration. the vm register resides in the psd and can be accessed at any time by the 80c32. (see the psd8xx data sheets.) heres what the 80c32 does upon power-up or reset: boot from boot flash memory csboot0 at address 0h perform a checksum of main flash memory download main flash memory from a host computer if needed and validate contents. figure 6. memory map, enhanced design at boot-up/isp memory map configuration after moving the main flash. the next step is to move the main flash memory from data space to program space. to do so, while executing out of the secondary flash mem- ory, write the value 06h to the vm register. you will now have the memory map shown in figure 7. 0000 2000 ffff 4000 ffff 2800 8000 c000 0000 0300 0200 2000 0400 ai03346b not to scale boot from here program space data space unmapped 32 kbytes csboot1/ees1 optional boot flash/eeprom 8 kbytes csboot0/ees0 optional boot flash/eeprom 8 kbytes unmapped 22 kbytes fs0 page 0 16 kbyte fs2 page 1 16 kbyte fs1 page 0 16 kbyte fs3 page 1 16 kbyte fs4 page 2 16 kbyte fs6 page 3 16 kbyte fs5 page 2 16 kbyte unmapped psd control register (csiop) 256 bytes optional sram (rs0) 2 kbytes 8xc51 ram swap = 0 unlock = 0 vm register = 12h e000 csboot3/ees3 optional boot flash/eeprom 8 kbytes csboot2/ees2 optional boot flash/eeprom 8 kbytes c000 fs7 page 3 16 kbyte lcd chip select (cslcd) 256 bytes
19/25 AN1178 - application note figure 7. memory map after moving the main flash memory to program space memory map configuration after setting the swap bit. next, we want to swap main and secondary flash memory and transfer execution to main flash memory segment fs0. to do so, the swap bit must be set to hi to re-map the boot flash memory segments csboot0/csboot1 out of the mcu boot area and replace it with main flash memory segment fs0, as shown in figure 8. so that no program continuity is lost, the instruction that sets the swap bit is executed from csboot0 and the next contiguous instruction must be in fs0. for example, if the instruction that executes the swap is at location 1000h in csboot0, then fs0 must contain the next instruction to be executed at location 1002h. 0000 2000 ffff 4000 ffff 2800 8000 c000 0000 0300 0200 2000 0400 ai03347b not to scale execute from here program space data space unmapped 54 kbytes csboot1/ees1 optional boot flash/eeprom 8 kbytes csboot0/ees0 optional boot flash/eeprom 8 kbytes unmapped 16 kbytes fs0 page 0 16 kbyte fs2 page 1 16 kbyte fs4 page 2 16 kbyte fs6 page 3 16 kbyte unmapped psd control register (csiop) 256 bytes optional sram (rs0) 2 kbytes 8xc51 ram swap = 0 unlock = 0 vm register = 06h e000 csboot3/ees3 optional boot flash/eeprom 8 kbytes csboot2/ees2 optional boot flash/eeprom 8 kbytes lcd chip select (cslcd) 256 bytes boot memory temporarily overlaps flash segments fs1, fs3, fs5 and fs7
AN1178 - application note 20/25 figure 8. memory map after setting the swap bit memory map configuration after moving the boot flash memory to data space. the final step is to move the secondary flash memory to data space so that it can be updated if desired. to move the secondary flash memory to data space, write 0ch to the vm register. once the vm register has been written, you can program either half of the secondary flash memory, depending on how the unlock bit is set. figure 9 shows the final state of the memory map. 0000 a000 ffff 4000 ffff 2800 8000 c000 0000 0300 0200 2000 0400 ai03348b not to scale execute from here program space data space unmapped 48 kbytes csboot1/ees1 optional boot flash/eeprom 8 kbytes csboot0/ees0 optional boot flash/eeprom 8 kbytes fs1 16 kbytes (flash sector 1) unmapped lcd chip select (cslcd) 256 bytes optional sram (rs0) 2 kbytes 8xc51 ram swap = 1 unlock = 0 vm register = 06h fs0 16 kbytes (flash sector 0) swap boot memory temporarily overlaps flash segments fs2, fs4 and fs6 boot memory temporarily overlaps flash segments fs3, fs5 and fs7 e000 csboot3/ees3 optional boot flash/eeprom 8 kbytes csboot2/ees2 optional boot flash/eeprom 8 kbytes psd control register (csiop) 256 bytes
21/25 AN1178 - application note figure 9. memory map after moving the boot flash memory to data space in this final configuration, the 80c32 has available: 32 kbytes main flash memory (fs0 and fs1) in the bottom of program space common to all pages 96 kbytes main flash memory in program space across three pages (8000h-ffffh) 2 kbytes of sram in addition to the sram that resides on the 80c32 16 kbytes of secondary flash memory for general data storage in data space (c000h-ffffh) 16 kbytes of secondary flash memory for boot and isp loader code in data space (8000h-ffffh). each time this 80c32 system gets reset or goes through a power-on cycle, the psd presents the memory map of figure 6 to the mcu, and the boot sequence is repeated. psdsoft express design entry the steps to implement the second design in psdsoft express are almost identical to those in the first design. in fact, you can repeat the steps outlined in sections 3.2.1 to 3.2.3, except you should give your new project a different name. then, when you are presented with the mcu template selection screen, you should select advanced iap, page & swap. differences to note: you will notice that in the page register definition screen in the design assistant, there are two new added bits: swap and unlock. these bits are used in the chip select equations to implement memory swapping and control of which secondary memory section is made available in data space. notice how 0000 a000 ffff 4000 ffff 2800 8000 c000 0000 0300 0200 2000 0400 ai03349b not to scale program space data space unmapped 22 kbytes csboot1/ees1 optional boot flash/eeprom 8 kbytes csboot0/ees0 optional boot flash/eeprom 8 kbytes fs1 16 kbytes (flash sector 1) not map- ped page 0 fs3 page 1 16 kbyte fs5 page 2 16 kbyte unmapped lcd chip select (cslcd) 256 bytes optional sram (rs0) 2 kbytes 8xc51 ram swap = 1 unlock = 0 or 1 vm register = 0ch fs0 16 kbytes (flash sector 0) e000 c000 csboot3/ees3 optional boot flash/eeprom 8 kbytes csboot2/ees2 optional boot flash/eeprom 8 kbytes 8000 fs2 page 1 16 kbyte fs4 page 2 16 kbyte fs7 page 3 16 kbyte fs6 page 3 16 kbyte psd control register (csiop) 256 bytes
AN1178 - application note 22/25 these two bits are defined as logic inputs to the pld instead of paging bits. the chip selects will now match the situational memory maps outlined in figure 6 to figure 9. that is, the memory map that is presented to the mcu varies dynamically based on the settings of the vm register and page register bits swap and unlock. for more information on both the page register and vm register, see the data sheets and the psdsoft express user manual . when mapping the 80c32 firmware in the address translate utility of psdsoft express for this second design example, you still do not need to specify any hex file for the psd main flash memory area. you only need to specify the 80c32 linker file(s) for the secondary flash memory area (as in the first simple design) because the 80c32 will execute code from secondary flash memory and download to main flash memory. conclusion these examples are just two of an endless number of ways to configure the easy flash ? psd for your system. concurrent memories with a built-in programmable decoder at the segment level offer excellent flexibility. also, as you have seen with the swap and unlock bits, the page register bits do not have to be used just for paging through memory. the ability to expand your system does not require any physical connection changes, as everything is configured internal to the psd. and finally, the jtag channel can be used for isp anytime, and anywhere, with no participation from the mcu. all of these features are crosschecked under the psdsoft express development environment to minimize your effort to design a flash 80c32 system capable of isp. references psd8xx family data sheets for detailed psd8xx information psdsoft express user manual for details on how to use the design software application note an1153jtag isp information: flash psd for detailed use of the jtag port appendix a: connecting to a psd813f with no boot memory the following is a sample memory map for connecting to a psd813f with no secondary memory (such as the psd813f3 or psd813f5). this memory map assumes you have downloaded the main flash memory with the flashlink cable or you have booted from a separate prom and have downloaded the flash memory using the mcu. in either case, you must change your design to account for the lack of secondary memory.
23/25 AN1178 - application note figure 10. memory map for a psd813f device (with no secondary boot memory) 0000 ffff 4000 ffff 4000 c000 0000 2000 0400 2900 2800 ai03350b not to scale program space data space fs1 16 kbytes (flash sector 1) fs3 page 0 16 kbyte fs5 page 1 16 kbyte fs7 page 2 16 kbyte not mapped page 3 16 kbyte unmapped 5.75 kbytes optional sram (rs0) 2 kbytes 8xc51 ram up to 1 kbyte fs0 16 kbytes (flash sector 0) 8000 fs2 page 0 16 kbyte fs4 page 1 16 kbyte fs6 page 2 16 kbyte not mapped page 3 16 kbyte unmapped 48 kbytes psd control register (csiop) 256 bytes unmapped
AN1178 - application note 24/25 table 1. document revision history date rev. description of revision aug-2000 2.0 document written in the wsi format 26-oct-2001 3.0 document converted to the st format
25/25 AN1178 - application note for current information on psd products, please consult our pages on the world wide web: www.st.com/psd if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.psd@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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